Present silicon (Si) nanometer (nm) scale electronic devices are constructed using planar FET topologies. The FET control gate is composed of a gate dielectric (usually an oxide and thus termed a ‘gate-oxide’) and is typically composed of silicon dioxide (SiO2) or silicon oxy-nitride (SiOxNy) dielectric materials disposed upon a single crystal silicon active layer and/or substrate. Modern logic design is based on complementary-metal-oxide-semiconductors (CMOS) employing charge carrier transport exhibiting both n-type and p-type CMOSFETs and are characterized by transistor feature sizes in ranges of 130 nm, 90 nm, 65 nm, 45 nm, 32 nm, and ultimately approaching 20 nm. Referring to FIG. 1, a graph is illustrated showing the actual and projected CMOSFET length scale and gate length (Lg) required as a function of technology generation (technology node) and year. As the planar transistor geometry shrinks in accordance with new fabrication generations or technology nodes, all the CMOSFET dimensions must scale. For example, the gate oxide thickness and gate length must also be reduced (or scaled) in accordance with well known scaling rules. The primary advantage of CMOS logic gates is the logic elements (composed of many nMOS and pMOS transistors) only draw significant current between logic state transitions, thereby allowing power consumption to be greatly minimized due to negligible dissipation in the off-state. This is clearly an advantage for high densities of logic elements in ultra-large-scale integrated circuits (ULSICs), such as, microprocessors and mobile and/or portable devices.
Projected performance gains of 30% per technology generation have been targeted at increasing CMOSFET density and circuit function per unit area. An added benefit of reduced feature scaling is that increased MOSFET device and overall circuit speed occurs. Ideal device performance has been relaxed due to deficiencies in materials and manufacturing methods available, resulting in CMOSFET sub-threshold leakage current increasing continuously from several nanoamperes per micrometer (nA/μm) at the 130 nm technology node, to currently hundreds of nA/μm at the 65 nm technology node. This leakage represents approximately two orders of magnitude increase in leakage power.
There are two types of leakage power in ULSICs: active leakage power and standby leakage power. Active leakage power is defined as leakage power consumed by a nanoscale CMOS system while doing useful work and standby leakage power is leakage power consumed when the system is idle.
The 90 nm technology node has seen leakage power increase to as much as 40% of the total on-chip power consumed. The waste heat and/or power dissipation situation degrades further with reduced CMOSFET length scaling to 65 nm and below. The leakage currents ultimately manifest as heat in ULSICs with large waste heat power densities and will soon exceed on-chip and off-chip conventional thermal management systems. Such large thermal loads result in reduced system reliability and place limits on the battery lifetime of portable devices. Ultimately, the thermal problem due to leakage currents places hard thermodynamic limits on further CMOSFET feature size reduction, circuit density and increased frequency of operation.
The leakage currents in planar single gate CMOSFETs can be generally classed as leakage substantially through the control gate oxide insulator and leakage between the channel layer and the substrate.
Sub-90 nm CMOSFET channel length scaling requires conventional gate oxide insulator thickness (LGOX) to approach only a few atomic layers. Such small physical thickness of LGOX is causing a failing of the ideal insulator action of the gate oxide due to quantum mechanical tunneling processes. This gate oxide tunneling current adversely affects the off-state and on-state leakage and the mobility of the fundamental carriers, electrons (nMOS) and holes (pMOS). Unfortunately, replacing the gate oxide with an ideal higher dielectric constant (i.e., high-κ) material in order to satisfy the equivalent gate oxide thickness (EOTGOX) required along with high reliability and fabrication compatibility has not yet eventuated despite much effort and research over the past decade.
Efforts to reduce channel to substrate leakage concentrated on implementing partially depleted semiconductor-on-insulator (PDSOI) substrates. Historically, PDSOI is used as a solution to reduce device leakage currents and substrate capacitance. Unfortunately, the early advantage of reduced capacitive coupling of the channel to the substrate using PDSOI when incorporated in long gate length devices above the 90 nm technology node has been superseded by more challenging factors for short channel CMOSFET dimensions below the 65 nm technology node.
Scaling below the 65 nm technology node imposes many new constraints on device topology. In order to retain the fundamental electrostatic operation of the CMOSFET devices below the 65 nm technology node, the use of fully-depleted semiconductor-on-insulator (FDSOI) substrates are necessary. Optimal FDSOI design relies on an understanding of the unique performance advantages provided by both the ultrathin semiconductor active layer (or body) and the buried insulator layer. Conventional semiconductor-on-insulator substrates use silicon-on-insulator (SOI) structure.
Classical bulk-Si and PDSOI CMOS scaling beyond a physical gate length of ˜50 nm will probably no longer be valid due to severe short channel effects (SCEs) and unacceptably low ratios between on and off currents (Ion/Ioff). This is the primary reason for introducing single gate (SG) FDSOI devices initially at 65 nm. Toward the 32 nm technology node, or approximately thereat, planar and/or vertical double gate (DG) FDSOI devices are required to preserve FET electrical integrity. Key issues effecting planar single gate FDSOI are the introduction of high-κ gate oxides, gate contacts (e.g., metal gates), FDSOI physical structure and manufacturability, source and drain contact resistance, and channel mobility.
One advantage not commonly remarked upon is the fact that SG FDSOI potentially simplifies the ULSIC front-end-of-line (FEOL) process and potentially the cost of manufacture. That is, bulk-Si and PDSOI CMOS typically use twin-wells to define the body of either the pMOS (using an n-well) and nMOS (using a p-well) because the substrate has a fixed conductive type. The gate threshold voltage can be adjusted via a n-doped (or p-doped) poly-Si gate contact stacked onto the gate oxide for n-MOS (or PMOS). P-type (or n-type) source and drain implants are used to realize p-MOS (or n-MOS) devices. It is well known by artisans in the field, the following FEOL steps are essential to the formation of the dual well CMOSFET process. First, a deep doping peak is formed using ion implantation techniques, so as to aid in the: (i) suppression of transistor latch-up; (ii) reduce charge pairs generated from radiation effects; and (iii) provide part of the electrostatic discharge protection path. The next critical FEOL step forms a shallow doping peak located just below the bottom of the shallow trench isolation regions separating FET devices. This step suppresses lateral leakage between adjacent transistors within the wells (intra-well leakage) and between adjacent transistors at the well boundaries (inter-well leakage). The next critical step forms another very shallow doping peak at the silicon surface and is used to set the threshold voltage Vth of the transistors. These steps are common to both bulk and PDSOI CMOSFETs.
The opportunity for fabrication process simplification using FDSOI mainly occurs in the three preceding steps outlined above. The use of FDSOI wafers eliminates the need for the high-energy ion implantation process that forms the deep n-type and p-type twin wells and the field channel stop isolation regions. This translates directly into fewer photolithographic masks and ion implantation steps, made possible by the elimination of well and field isolation implants.
CMOS transistors designed for use with SOI wafers are classified by thickness (designated LSi) of the device-quality single-crystal silicon layer at the surface of and extending above the buried oxide (BOX) insulator layer. The BOX layer is disposed upon a substrate, typically also composed of single crystal silicon. An SOI CMOS transistor is classified as partially depleted (PD) if the silicon surface layer is thicker than the depth of the depletion region (designated LDepl) in the transistor channel, i.e., LDepl<LSi. The SOI CMOS is classified as fully depleted (FD) if the silicon surface layer is equal to the depth of the depletion region in the transistor channel, i.e., LDepl=LSi. Examples of short channel and long channel FDSOI CMOSFET are illustrated in FIGS. 2A and 2B, respectively. The transistor will be partially depleted or fully depleted depending on the silicon layer thickness above the BOX and the doping concentration in the channel, designated Nch.
To form a FDSOI transistor, Nch must be low enough so that the gate depletion region extends throughout the entire thickness of the silicon active layer. When the silicon surface layer in the SOI CMOS is thicker than about 50 nm (LSi>50 nm), the transistor will typically be partially depleted, unless Nch is reduced to such low values that Vth is too low for practical CMOS applications. If the silicon layer thickness is reduced to LSi<50 nm, the transistor will be fully depleted, even when Nch is increased to produce Vth considerably higher than bulk and PDSOI devices. If the silicon layer thickness is reduced further toward and below LSi<20 nm, the transistor will remain fully depleted even if Nch is increased considerably to produce even higher threshold voltages (e.g., Vth˜700 mV).
Significant advantages exist for FDSOI transistors over PDSOI transistors, and the trend in SOI CMOS beyond 90 nm is toward the use of FD devices. A fundamental advantage in FDSOI CMOSFETs, is the parameter known as the subthreshold slope (SS), which can attain values that can be very low compared with bulk Si and PDSOI CMOSFETs. Typically, in FDSOI, a relatively small gate voltage, on the order of ˜50 mV increase, will result in a large, tenfold increase, in the subthreshold drain current. This allows Vth of the FDSOI CMOS device to be very low and to result in acceptable subthreshold leakage or off-state current (Ioff). The low Ioff determines the off-state power dissipation. Lowering Vth allows the supply voltage (Vs) to also be reduced significantly without degrading CMOS IC speed performance. This is a fundamental property of FET scaling. A general rule of thumb requires Vs to be greater or equal to 5Vth. Typically, for Vs<5Vth the speed performance of the circuit will degrade rapidly. The reduction of Vs produces a significant reduction in active power dissipation, without high performance degradation. Note, the active power dissipation is further reduced by reduction of parasitic capacitance in SOI CMOS relative to bulk CMOS.
In general, PDSOI CMOSFETs suffer problematic floating body effects, which is less of a problem in FDSOI transistors. Consequently, it is expected that FDSOI CMOS transistors will be generally adopted in the near future. Converting an existing PDSOI CMOS device and circuit design into FDSOI CMOS is expected to be straightforward, at least in comparison with the challenges in the conversion from bulk CMOS to SOI CMOS.
Using FDSOI devices, the short-channel effect is primarily controlled by the thickness of the silicon film (LSi), generally, the thinner the film, the better the control. Less than 20 nm of silicon should be used at the 90 nm technology node and less than 15 nm of silicon should be used at the 65 nm technology node for planar single-gate fully depleted transistors. Toward the end of the technology roadmap represented by the 20 nm technology node, only LSi˜5 nm is required. This represents significant manufacturing hurdles using conventional separation by implantation of oxygen (SIMOX) and wafer bonding techniques. Direct epitaxial techniques may provide significant advantages to SOI structure flexibility, uniformity and cost.
The electrostatic integrity (EI) advantage of single gate planar FDSOI MOSFETs compared to bulk Si MOSFETs is well known. FIG. 3 shows how the dimensionless figure of merit EI of planar single gate bulk Si, planar single gate FDSOI and double gate FDSOI MOSFETs scale as a function of the technology node. The required LSi for SG and DG FDSOI MOSFETs is also shown on the left hand axis of FIG. 3 as a function of the technology node.
Clearly, with reference to EI performance, the advantage of the SG FDSOI device is that it has substantially lower value of EI compared to bulk-Si for all technology nodes. Bulk-Si exhibits an unacceptably high value of EI (EI˜0.14) approaching and beyond the 65 nm technology node. The EI of SG FDSOI at the 45 nm technology node becomes equivalent to bulk-Si at the 65 nm technology node. SG and DG FDSOI structures are required to have ultra-thin Si body layer thickness in the range of 4 nm≦LSi≦25 nm, the mid to lower bound approaching the 20 nm technology node exhibiting quantum confinement effects. In prior art, LSi has typically been treated with the design parameters of the buried oxide (BOX) insulating layer as semi-infinite in extent. That is, the BOX layer has typically remained unchanged in the thick layer regime, LBOX>50-100 nm. The BOX layer is typically thick (tBox≦50-100 nm) so that the channel to BOX capacitance (CBOX) is kept small relative to the gate oxide capacitance (CGOX), such that CBOX<<CGOX. The trade-off between the short-channel effect, drain-induced barrier lowering and CBOX by varying the BOX layer thickness (tBox) and dielectric constant have not been investigated in depth.
Furthermore, for FDSOI substrates both the Si and BOX layers have a roadblock for manufacture using prior art techniques approaching 2011, with 15 nm≦LSi≦28 nm and 26 nm≦LBOX≦44 nm {itrs}. Thickness non-uniformity in both the Si and BOX layers is an important parameter for guarantee of MOSFET performance across a wafer. Therefore, techniques that allow relaxation of design manufacture tolerances are necessary to reduce cost and increase yield.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide new and improved methods and apparatus for controlling short channel effects, leakage, and threshold effects of FDSOI MOSFETs including various combinations and positions of multilayer thin BOX, low-κ designs, and high-κ designs.
An aspect of the present invention is to disclose methodology for controlling short channel effects and/or leakage and/or threshold effects of FDSOI MOSFETs advantageously using multilayer thin BOX and/or low-κ designs.
Another aspect of the present invention is to disclose methodology for controlling short channel effects and/or leakage and/or threshold effects of FDSOI MOSFETs advantageously using multilayer thin BOX and a combination of low-κ and high-κ designs.
A further aspect of the present invention is to disclose methodology for controlling short channel effects and/or leakage and/or threshold effects of FDSOI MOSFETs advantageously using multilayer thin BOX and/or low-κ designs with a conducting layer or layers disposed between the BOX layers and the substrate.